MRAM devices have become the subject of increasing interest, in view of the discovery of magnetic tunnel junctions having a strong magnetoresistance at ambient temperatures. MRAM devices offer a number of benefits, such as faster speed of writing and reading, non-volatility, and insensitivity to ionizing radiations. Consequently, MRAM devices are increasingly replacing memory devices that are based on a charge state of a capacitor, such as dynamic random access memory devices and flash memory devices.
In a conventional implementation, a MRAM device includes an array of MRAM cells, each one of which includes a magnetic tunnel junction formed of a pair of ferromagnetic layers separated by a thin insulating layer. One ferromagnetic layer, the so-called reference layer, is characterized by a magnetization with a fixed direction, and the other ferromagnetic layer, the so-called storage layer, is characterized by a magnetization with a direction that is varied upon writing of the device, such as by applying a magnetic field. When the respective magnetizations of the reference layer and the storage layer are antiparallel, a resistance of the magnetic tunnel junction is high, namely having a resistance value Rmax corresponding to a high logic state “1”. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction is low, namely having a resistance value Rmin corresponding to a low logic state “0”. A logic state of a MRAM cell is read by comparing its resistance value to a reference resistance value Rref, which is derived from a reference cell or a group of reference cells and represents an in-between resistance value between that of the high logic state “1” and the low logic state “0”.
In a conventional MRAM cell, a reference layer is typically exchange biased by an adjacent antiferromagnetic layer, which is characterized by a threshold temperature TBR of the antiferromagnetic layer. Below the threshold temperature TBR, a magnetization of the reference layer is pinned by the exchange bias of the antiferromagnetic layer, thereby retaining the magnetization of the reference layer in a fixed direction. Above the threshold temperature TBR, the exchange bias substantially vanishes, thereby unpinning the magnetization of the reference layer. Consequently, and in order to avoid data loss, an operation temperature window of the conventional MRAM cell has an upper bound defined by the threshold temperature TBR.
In the case of a MRAM cell that is implemented for thermally assisted switching (“TAS”), a storage layer also is typically exchange biased by another antiferromagnetic layer, which is adjacent to the storage layer and is characterized by a threshold temperature TBS that is smaller than the threshold temperature TBR. Below the threshold temperature TBS, a magnetization of the storage layer is pinned by the exchange bias, thereby inhibiting writing of the storage layer. Writing is carried out by heating the MRAM cell above the threshold temperature TBS (but below TBR), thereby unpinning the magnetization of the storage layer to allow writing, such as by applying a magnetic field. The MRAM cell is then cooled to below the threshold temperature TBS with the magnetic field applied, such that the magnetization of the storage layer is “frozen” in the written direction.
While offering a number of benefits, a conventional TAS-type MRAM device suffers from certain deficiencies. Specifically, a write operation temperature window is defined by TBR−TBS and, therefore, is bounded by the threshold temperature TBR at the upper end and the threshold temperature TBS at the lower end. Because of practical constraints on antiferromagnetic materials for exchange bias, the write operation temperature window can be rather limited, such as to a range less than 200° C. or less than 150° C. Moreover, in the case of an array of TAS-type MRAM cells, characteristics of individual cells can vary across the array due to manufacturing variability. This variability can result in a distribution of the threshold temperatures TBS and TBR for the array, which, for example, can amount up to ±30° C., thereby further reducing the write operation temperature window. In addition, this variability can impact a resistance of magnetic tunnel junctions across the array and can result in a distribution of the resistance values Rmin and Rmax for the array, thereby complicating a comparison between a measured resistance value of an individual cell and a reference resistance value Rref during reading. Consequently, a tight tolerance control can be required during manufacturing, and this tight tolerance control can translate into lower manufacturing yields and higher manufacturing costs.
It is against this background that a need arose to develop the memory devices and related methods described herein.